Chip set for Pentium 4

In competitive struggle the leader of the computer industry Intel corporation at last realised the project on development and release of the 32-bit processor with essentially new architecture. Not wishing to refuse the advertised brand and according to the installed traditions, the new product has received a name of Pentium 4. Whether the new favourite of waiting of implementators and users will justify — will show time and … careful testing which, by the way, has already started.

As a result of the led testing there were first estimations and critical remarks. But it is a subject of separate research and is not the task of given article. Here it is necessary to mark, that implementation of arrogant schedules of implementators has demanded not only radical processing of an inner pattern of the processor, but also depositing of respective alterations in the architecture of the computer and development of appropriate units of a surrounding — chip sets.

First of all changes have concerned processor buses. To nobody a secret what exactly this unit of the architecture of system often is a bottleneck in reaching of high values of computer power. Insufficient capacity of this bus is quite often accompanied nedozagruzkoj the processor at the expense of appearance of additional cycles of waiting of readiness of the bus. The processor overall performance as a result decreases. Especially it concerns high-powered processors with high values of internal operating frequencies. The given circumstance is well known to experts. For this reason to growth of productivity of processors in the architecture there was an increase in digit capacity of the bus of the processor before 64-bits and frequency its operations to 133 MHz. However further growth clock frequency is inconvenient also implementators have selected other path of rise of capacity of the bus of the processor. AMD corporation became the first. Since processors AMD Athlon, this corporation uses bus Alpha EV6 developed by DEC corporation and not compatible with traditional GTL + and AGTL +. Bus Alpha EV6 carries out data transfer on front and back fronts of clock pulses. It allows to provide at clock rate of 100 MHz data transfer with frequency of 200 MHz, and at 133 MHz — 266 MHz. Has not stood aside of the given tendencies and Intel corporation. Together with the processor of Pentium 4 it inserts the bus which at clock rate of 100 MHz carries out data transfer with frequency of 400 MHz.

Such novovedenie depositing corresponding korrektivov in the architecture of the computer and development of appropriate units of a surrounding of the processor has demanded.

As is known, implementation of considerable potential possibilities of modern high-powered processors in the big degree depends on their electronic surrounding, for example, from integral chips environing the processor and other radioelements. The given chips and units set necessary working conditions of power supplies and data transfer, that is provide effective operation of the central processor unit. They also carry out electrical and logical links of the processor and other parts of all system of the computer, influencing on the common productivity. The given chips of a surrounding of the processor are presented now by the specialised chipset of system logic named as a chip set (chipset).

The chip set, its inner pattern and functionality should be closely co-ordinated to features of the architecture of concrete variants of processors, with which they are oriented to operation. For the processor of Pentium 4 such chip set became i850.

The chip set i850 (i850 Сhipset) is continuation of a line of specialised chipsets of system logic of the corporation of Intel as which ancestor has served i810 (i810 Chipset). It is optimised for processors of Intel of Pentiums 4 working at clock rate of the bus of processor Host Bus (FSB) of 100 MHz (400 MHz Data Bus).

The chip set structure i820, as well as its predecessors, is based on usage habovoj architectures which allows to optimise structure of the computer and to accelerate an informational exchange between arrangements with the minimum loading of the processor for similar operations. Besides, given structure allows to change easily functionality of system at the expense of change of the chipset (hubs).

As the main bus for interconnection of the hubs which are a part of a chip set, the 8-bit wire providing capacity to 266 Mb per second is applied specially developed, closed .

The built in interface of operation with memory (DRAM interface) supports two channels of memory of processing technique Direct Rambus. Clock rate of the channel — 300 and 400 MHz. The transmission frequency of data which is carried out on front and back fronts of a clock signal, at clock rate of the channel of 400 MHz as a result of such processing technique reaches 800 MHz. It provides a transfer rate of 1,6 Gbytes/with for each channel, that at usage of two-channel structure of a subsystem of memory of a chip set i850 allows to reach 3,2 Gbytes/with.

Maximum memory size DRDRAM (Direct Rambus DRAM), presented by RIMM units, can reach 1 values of Gbytes at usage of chips of 128 bits and 2 Gbytes — at 256 bits.

Built in structure of a chip set interface AGP ensures functioning of one arrangement AGP with support of modes 1X/2X/4X. The AGP-arrangement can be external or integrated into the motherboard architecture.

Handle of peripheral devices carries out an input-output hub (I/O) — I/O Controller Hub (ICH2). Structure ICH2 includes following controllers: the interface with MCH, 2-channel UltraDMA/100 IDE (4 arrangements IDE, reading to 100 Mb per second, writing to 89 Mb per second), 2 USB (only 4 ports), I/O APIC, SMBus, the interface with FWH, LPC (allows to hook up arrangements ISA and X-Bus, such as Super I/O, controllers of the keyboard, the flexible drive, parallel, consecutive ports), AC ’ 97 2.1 (to 6 channels of audio), PCI 2.2 (to 6 arrangements PCI), LAN (c Intel 82562EH — 1 Mbit/with HomePNA, Intel 82562ET — 10/100 Mbit/with Ethernet), System and Power Management.

The base variant of a chip set i850 consists of three chips: 82850 Memory Controller Hub (MCH) in konstruktive 615 OLGA (13x35 mm), 82801BA I/O Controller Hub (ICH2), 82802 Firmware Hub (FWH).

Systems on the basis of a chip set i850 possess high efficiency and wide functionality. The given chip set, apparently, is intended to substitute step-by-step unpopular and less efficient i820, and also to draw attention and to revive dying away interest to processing technique of memory Rambus.