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Classification, imenovanie and short parametres of processors

< P>In the technical literature, press releases, and also in preliminary announcements of implementators and manufacturers code names of processors and their architectures quite often use. However after the official declaration the same products become already known under other names. Thus from marketing reasons to the processors created on different processing technique and having differences in the architecture of the kernels, identical names are often assigned. Such state of affairs will disorganise not only novice users, but is frequent also experts.

Attempt of classification and decryption of firm (trade marks) and code names of processors, and also their kernels with coercion of short characteristics is more low presented. As a basis article with addition of the substances published on sites and in the firm documentation of manufacturers is used.

In the resulted data separate inaccuracies which will be considered and corrected in the future versions of this and similar articles can contain.


Pentium – the first processors of P5 set (March, 1993). Then Intel not to repeat an error with i486 (the court has rejected the claim to AMD concerning the name), has decided to name the product which became subsequently nominal. Pentium first generation carried code name P5, and also i80501, the supply voltage was 5 In, layout of outputs – "matrix", clock frequency – 60 and 66 MHz, manufacturing techniques – 0,80-micron, frequency of the bus is equal to frequency of a kernel. Were released in konstruktive under Socket 4.

Development of this set became P54, it i80502, the kernel supply voltage has been lowered with 5 In to 3,3 In, layout of outputs – "a chess matrix", processing technique – 0,50 microns, and then 0,35 microns. Clock rate of a kernel – 75-200 MHz, buses – 50, 60, 66 MHz. Cache memory L1 size 16Кбайт. For the first time it has been divided – 8 Kbytes into the given and 8 Kbytes on instructions. Socket 7 plug. IA32 architecture, the instruction set did not vary since times of processors i386.

Pentiums MMX (P55, January, 1997) became following processors of the corporation of Intel. The new set from 57 MMX commands was added. Processing technique – 0,35 microns. The kernel supply voltage has decreased to 2,8 V.Protsessory change in the architecture of motherboards as double power supplies have demanded installation of an additional surge protector have demanded. Cache memory L1 size has been increased twice and has made 32 Kbytes. Internal clock rate 166-233 MHz, frequency of the bus – 66 MHz. Are calculated on Socket 7. Became last in the bar of processors of Pentium for computers Desktop.

Tillamook – the code name of a kernel of processors of Pentiums created in January, 1997 Are intended for application in laptops. Processing technique – 0,25 microns. Differ a kernel and power-dissipation capability reduced voltage. Cache memory L1 – 32 Kbytes, instruction set MMX. Clock frequency from 133 to 266 + MHz with frequency of the bus of 60-66 MHz. Packing type TCP and MMC. There are adapters for installation Tillamook in slot Super 7.

Pentium Pro – the first processors of the sixth generation released in November, 1995 For the first time cache memory L2 banked in one tank with a kernel and working on frequency of a kernel of the processor is applied. Processors had very high cost price of manufacture. 0,50 microns, and then on 0,35 microns that has allowed to increase size of cache memory L2 with 256 to 512, 1024 and 2048 Kbytes were released at first on processing technique. Clock rate from 150 to 200 MHz. Frequency of the bus – 60 and 66 MHz. Cache memory L1 – 16 Kbytes. Socket 8 plug. Supported all instructions of processors of Pentium, and also a number of new instructions (cmov, fcomi etc.). The double independent bus has been entered Into the architecture (DIB). Further all innovations have inherited Pentium II. The architecture of Pentium Pro has considerably anticipated time.

Pentiums II/III – P6/6x86 set, the first representatives have appeared in May, 1997 the Set of these processors banks under the common name the processors intended for different segments of the market: Pentium II (Klamath, Deschutes, Katmai) – for the mass market of the PC of an average level, Celeron (Covington, Mendocino, Dixon etc.) – for inexpensive computers, Xeon (Xeon, Tanner, Cascades etc.) – for high-powered servers and workstations. Has modifications for Slot 1, Slot 2, Socket 370, and also appropriate variants for transportable computers.

Klamath – the name of a kernel of the first processors of the bar of Pentium II (January, 1997). Processing technique – 0,35 microns. Clock frequency kernels – 233-300 MHz. Frequency of the bus – 66 MHz, cache memory L1 – 32 Kbytes, cache memory L2 – 512 Kbytes. Last for processor depreciation it is allocated on the processor card and works on half frequency processor kernels. It is added by the MMX-block. Kernel power supply 2,8 In, konstruktiv cartridge SECC, the plug – Slot 1.

Deschutes – the kernel name (January, 1998) processors of the bar of Pentium II which have replaced Klamath. Processing technique – 0,25 microns, kernel power supply 2,0 266-450 + MHz, frequency of the bus – 66, 100 MHz, cache memory L1 – 32 Kbytes, cache memory L2 allocated on the card of the processor, – 512 Kbytes. The plug – Slot 1. Konstruktiv cartridge SECC which in high models has been replaced on SECC2 (a cache memory on the one hand from a kernel, instead of from two, as in standard Deschutes; the changed mount of a cooler).

Tonga – one of code names of transportable processors of Pentium II – Mobile Pentium II. It is constructed on 0,25 microns kernel Deschutes. For the first time there was in April, 1998 a Clock rate of a kernel – 233-300 + MHz, buses – 66 MHz. It was released in konstruktive Mini Cartridge Connector and Mobile Module Connector 1 and 2 (MMC-1 and 2).

Katmai – the kernel name (September, 1999) processors of Pentium III which have come in the stead Deschutes. Block SSE is added (Streaming SIMD Extensions), is expanded instruction set MMX, is improved the mechanism of stream memory access. Tehprotsess 0,25 microns, clock rate 450-600 MHz, cache memory L2 allocated on the processor card, – 512 Kbytes. Frequency of the bus – 100 MHz, but in connection with delay Coppermine have been released models 533 and 600 MHz calculated for frequency of the bus of the processor of 133 MHz.

Celeron – the set of the processors oriented to the mass market of inexpensive computers. This set includes the models created on the basis of Covington architectures, Mendocino, Dixon, Coppermine. For the first time have appeared in April, 1998. Were released in the beginning for Slot 1, further – for Socket 370.

Covington – the first variants of processors (April, 1998) bars Celeron. Are constructed on kernel Deschutes. Processing technique – 0,25 microns. Clock rate 266-300 MHz, frequency of the bus – 66 MHz, cache memory L1 – 32 Kbytes. For reduction of the cost price processors were released without the cache memory of the second level and a protective cartridge. Kernel power supply 2,0 V.Interfejs – facilitated Slot 1, konstruktiv SEPP (Single Edge Pin Package). Processors were characterised rather by low output, but, thanks to absence of cache memory L2, differed high stability of operation in dispersal modes.

Mendocino – the kernel name (August, 1998) bar Celeron processors. Has cache memory L2 in size of 128 Kbytes, integrated into a chip of the processor and working on frequency of a kernel thanks to what high efficiency is provided. Clock rate 300-533 MHz, frequency of the bus – 66 MHz. Considering, that in the market already there was a processor with frequency of 300 MHz, the first model of the processor which were created on the basis of kernel Mendocino and having the same frequency, has received name Celeron 300A. Processing technique – 0,25 microns. Kernel power supply 2.0 V.Pervonachalnyj form factor Slot 1 (300-433 MHz) has step-by-step been superseded Socket 370 (300-533 MHz).

Dixon – the kernel name, and also a code name of the processors oriented to application in laptops. Processing technique – 0,25 microns, further – 0,18 microns. Size of the cache memory of the first level – 32 Kbytes. As well as in Mendocino, cache memory L2 is allocated on the chip, however its size is increased to 256 Kbytes. Clock rate 300-500 MHz, frequency of the bus – 66 MHz. Official classification – transportable processors of Pentium II.

Coppermine – the name of a kernel of processors of Pentium III and Celeron. Processing technique – 0,18 microns. It is characterised by presence of the processors of 256 Kbytes of cache memory L2 integrated on chips for Pentium III and 128 Kbytes – for Celeron. Frequency – from 533 MHz and above. Along with FSB100 MHz versions of Pentium III release also variants FSB133 MHz. The last processors calculated on Slot 1, have step-by-step been superseded by products in konstruktive FC-PGA 370, calculated for Socket 370 plug. Frequency of the bus for processors Celeron – 66 MHz, and since model Celeron 800 – 100 MHz. A kernel supply voltage from 1,5 In to 1,7 Century

Coppermine T – the name of a kernel of processors of Pentium III and Celeron. Is a transitive step from Coppermine architecture kernel to Tualatin architecture kernel. It is created on processing technique 0,18 microns. It is oriented to operation with the chip sets supporting processors with kernel Tualatin.

Tualatin-256K – The code name of a kernel and processors Socket 370 Pentiums III made on 0,13 microns tehprotsessu. These are last Pentiums III. Differ from Coppermine more perfect architecture and the "know-how". Are characterised by a reduced voltage of power supply and smaller energopotrebleniem. The Operating frequency of models for Desktop with FSB 100 MHz – 1,0, 1,1 GHz, and with FSB 133 MHz – 1,13 GHz and above.

Tualatin-512K – The code name of a kernel and processors. Contains kernel Tualatin, but has 512 Kbytes of cache memory L2. Processors are intended only for the transportable arrangements, appropriate versions for Desktop are not planned not to compete to Pentium 4. In the architecture of the processors created on the basis of kernel Tualatin-512K, support of processing techniques energosberezhenija is carried out. Standard power of a kernel – 1,4 In and more low. On the end of 2001 new generation release on kernel Tualatin with FSB 100/133 MHz for economic models mini-and subnotebooks is planned.

Tualatin-512K DP – the code name of a kernel and processors for servers and workstations. Release of the first models with an operating frequency of 1,13 GHz and 1,26 GHz is planned on second half of 2001

Pentium III-M – the transportable processors of a new generation made with usage of a 0,13-micron procedure. Have new controls energopotrebleniem SpeedStep, Deeper Sleep, etc. Standard power of a kernel – 1,4 In and more low.

Pentium III-S – processors with kernel Tualatin, processing technique – 0,13 microns, cache memory L2 – 512 Kbytes, workers frequency – about 1,13 GHz. Are intended for dual-processor patterns.

Timna – the code name of the processors created on the basis of kernel Coppermine with cache memory L2 of 128 Kbytes, integrated on the chip a graphics kernel and the dynamic storage controller. Are oriented on supercheap PC and teleprefixes. Release is excellent the corporation of Intel owing to hopelessness of a product.

Banias – the code name of the processors, which architecture it is similar with Timna. The computing kernel of the processor, a graphics kernel, and also northern bridge of a chip set are integrated Into the chip. Unlike Timna support RDRAM is not provided. It is supposed, that except the version with standard power supply variants Low Voltage and Ultra Low Voltage will be released.

Development of project Banias is carried on in Israeli Intel Israel Design Center, the beginning of mass production of the processor is planned on the end of 2002 – the beginning of 2003. The updated architecture of Pentium III is put in a basis of a kernel of new processor Banias, but without the hyperpipeline organisation inherent in processors of Pentium 4. Processors Banias will be released in the modifications inherent in present classes of transportable processors from Intel, namely Pentium III/Low-Voltage Pentium III/Ultra-Low-Voltage Pentium III. The special processing technique of intraprocessor interconnections MicroOps Fusion is developed For reduction of energy consumed by the processor. The first chips will have clock rate since that on which, most likely, will stop transportable Tualatin-M - 1,4 GHz. However, the economic processor will find a place and in servers where the problem of consumption of energy and a heat release also takes not the last place.

As project head Banias has underlined, before the command is put three overall objectives: reduction of the sizes of transistors for lowering of consumed energy, development of effective processing technique of rise clock frequency without essential increase in consumed energy, development of effective processing technique of operation with commands of the processor.

Xeon – the official name of the bar of the processors oriented to usage as a part of powerful servers and workstations.

The first variants have been constructed on kernel Deschutes. Are changeover of processors of Pentium Pro. Processing technique – 0,25 microns. Processor Slot 2 plug. Processors of this type are capable to work in multiprocessor patterns. Cache memory L2 has size 512, 1024, 2048 Kbytes, that in many respects defines high cost and a heat release.

In the course of processing technique perfection release of different models of processors of Intel of Pentium III Xeon on the basis of kernel Coppermine with step-by-step transition to Tualatin architecture is carried out.

The first models on Tualatin architecture: Intel of Pentium III Xeon DP (DP – double processor) – power on a kernel 1,10-1,15 In, tehprotsess 0,13 microns, 512 Kbytes L2, 133 MHz FSB, chip sets ServerWorks HE-SL and ServerWorks LE-3; Intel of Pentium III Xeon MP (MP – multiprocessor) – 1 Mb L3 on a chip for 8-processor systems and 512 Kbytes L3 on a chip for 4-processor systems, 1,60 GHz and above.

Server variants of the processors constructed on the basis of the architecture of Pentium 4 with kernel Foster, have received the name of Intel Xeon. The first representatives of these processors have working frequency 1,7 GHz and are calculated for Socket 603 plug usage. Originally are intended for workstations of the higher and middle class with support of dual-processor patterns. Support of operation of Intel Xeon is carried out by a chip set i860, which price considerably above the price i850, Pentium used together with processors 4.

Tanner – the code name of Pentium III Xeon. It is intended, first of all, for High-End servers. Clock rate from 500 MHz, frequency of the system bus of 100 MHz, the CSRAM-L2 cache in size 512, 1024 and 2048 Kbytes works on frequency of the processor. Cache memory L1 – 32 Kbytes is supported MMX and SSE.

Cascades – the code name of Pentium III Xeon, 0,18 microns created on the basis of a procedure. Is server variant Coppermine. On the chip cache memory L2 of 256 Kbytes, clock rate from 600 MHz, frequency of the bus of the processor – 133 MHz contains. The first variants work only in dual-processor patterns and only on frequency of the system bus of 133 MHz. In the end of 2000 cache memory L2 size on the chip has been increased to 2 Mb. Final clock rate 900 MHz for the high-grade version, 1 GHz – for the version from 256 Kbytes L2. The Form factor – Slot 2.

Pentium 4 – the following after Coppermine essentially new IA-32 processors of Intel for usual PC. Instead of traditional GTL + and AGTL + the new system bus Quad Pumped of 100 MHz providing data transfer with frequency of 400 MHz and transmission of addresses with frequency of 200 MHz uses. Cache memory L1 – 8 Kbytes, L2 – 256 Kbytes. A number of the refinements routed on increase clock frequency and productivity is entered into the architecture. The new set of instructions SSE2 is entered. The first models on the basis of kernel Willamette with clock rate of 1,4-1,5 GHz are released on October, 20th, 2000. The plug – Socket 423. The last model is calculated for frequency of 2 GHz then kernel Willamette replaces Northwood.

Willamette – the name of the first kernel of processors of Pentiums 4 created on processing technique of 0,18 microns.

Northwood – the name of a kernel of processors of Pentiums 4 created on processing technique of 0,13 microns. To implantation of this kernel there is a transition to new form factor Socket 478. The cache memory size is increased to 512 Kbytes. This processor should become the main in Intel assortment for long time, having replaced on this post bar Katmai/Coppermine. Initial clock rate 2,2 GHz.

Foster – the code name of a kernel and processors of Pentium 4 in the server variant, constructed on ideology and Willamette architecture. Clock rate 100 MHz at data transfer with frequency of 400 MHz. As well as in a case with Cascades, the size of cache memory L2 remained the same, that for Willamette. Main differences Foster from usual Pentiums 4 on kernel Willamette consist in support of dual-processor patterns and Socket 603 plug usage. Clock rate of first processors Xeon on kernel Foster starts from 1,7 GHz. The basis of systems will be made by chip sets i860 and GC-HE from ServerWorks. In 2002 architecture translation is planned for processing technique 0,13 microns. Then the new version Foster containing an additional cache memory of the third level will be released also.

Prestonia – the code name of a kernel and processors of Pentium 4 in the server variant, 0,13 microns created on processing technique. Bar Xeon continuation. Microarchitecture NetBurst. Development is carried on on the basis of kernel Foster which will be substituted by this new kernel in future processors Xeon. The basis of systems will be made by special chip set Plumas. Release is planned on first half of 2002. Frequency of the first models of the processor – 2,20 GHz.

Gallatin – the code name of a kernel and processors, 0,13 microns – development of kernel Foster. The output is planned on the end of 2002

Merced – the code name of a kernel and the first processor of IA-64 architecture, is hardware is compatible to IA-32 architecture. Includes the three-level cache memory in size of 2-4 Mb. Productivity approximately three times above, than for Tanner. Manufacturing techniques – 0,18 microns, frequency of a kernel – 667 MHz and above, frequency of the bus – 266 MHz. Exceeds Pentium Pro on operations FPU in 20 times. The physical interface – Slot M. Supports MMX and SSE2. The official name – Itanium.

Itanium – the trade mark under which the 64-bit processor earlier known under code name Merced is announced.

McKinley – the code name of a kernel and models of the second generation of processors of IA-64 architecture. Clock rate of a kernel of processors starts about 1 GHz. Productivity, in comparison with Merced Is supposed, that, capacity of the data bus having resultant frequency of 400 MHz, – three times will increase twice, and. McKinley will have increased in comparison with Merced size of the L2 cache and speed of operation. Power consumption will make 150 W. The physical interface – Slot M.

Madison – successor McKinley. It is planned to an output in 2002-2003 It is constructed on copper, 0,13 microns of processing technique.

Deerfield – the code name of a kernel and processors. The output is expected in 2003. Will be made on copper, 0,13 or 0,1 microns of processing technique of Motorola with usage of isolation with low number k and SOI (HiP7). The kernel is successor Foster. Processors are calculated on Slot M and taken up a position as inexpensive processors of IA-64 architecture for workstations and average level servers. Probably, the processors created on the basis of kernel Deerfield, become high-end processors of the user's market.

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To pass to razrelu Processors

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