Classification, imenovanie and short parametres of processors
(Continuation)

K5 – The first processors AMD announced as the competitor of Pentium. The plug – Socket 7. Similarly Cyrix 6x86, used a PR-rating with metrics from 75 to 166 MHz. Thus used frequency of the system bus made from 50 to 66 MHz. Cache memory L1 – 24 Kbytes (16 Kbytes for instructions and 8 Kbytes for data). Cache memory L2 is allocated on the motherboard and works on frequency of the processor bus. К5 stepping 0 had a code name "SSA5", and for steppingov 1, 3, 5 was a code name "5k86".

K6 – The processors announced as the competitor of Pentium II. The first models were made on processing technique 0,35 microns, further – 0,25 microns (a code name "Little Foot"). Processors worked on frequency from 166 to 233 MHz. Have been created on the basis of design of the processor 686 from gained AMD companies NexGen. On matching with the predecessors have received MMX unit, the size of cache memory L1 – to 64 Kbytes (on 32 Kbytes for instructions and data) has increased.

K6-2 – Following generation K6 with a code name "Chomper". The processor has quitted in May, 1998, the main refinement is support of an additional set of instructions 3DNow! And frequency the system bus of 100 MHz. Cache memory L1 – 64 Kbytes (on 32 Kbytes for instructions and data), cache memory L2 is on the motherboard and can have size from 512 Kbytes to 2 Mb, working on frequency of the bus of the processor. The first models had frequency of a kernel of 266 MHz.

K6-2 + – one of last Socket 7 processors AMD. And the first Socket 7 processors made with usage of 0,18 microns tehprotsessa.

K6-III (Sharptooth) – the first processors from AMD, having cache memory L2 banked with a kernel. The last processors made under platform Socket 7. Actually, represent simply K6-2 from 256 Kbytes cache memory L2 on the chip, working on the same frequency, as a processor kernel. Cache memory L1 has size of 64 Kbytes (on 32 Kbytes for instructions and data), cache memory L3 is on the motherboard and can have size from 512 Kbytes to 2 Mb, working on frequency of the bus of the processor. The first models released in February, 1999, have been calculated for 400 and 450 MHz.

Argon – the code name used in K7 kernels.

K7 – The first processors, the architecture and which interface differ from Intel. Cache memory L1 size – 128 Kbytes (on 64 Kbytes for instructions and data). Cache memory L2 – 512 Kbytes, working on 1/2, 2/5 or 1/3 frequency the processor. The processor bus – Alpha EV-6. Clock rate of the bus – 100 MHz with data transfer at 200 MHz. Supported sets of instructions – MMX and expanded in comparison with K6-III a set 3DNow!. The Form factor – Slot A. Has received name Athlon. MHz models 500-1000 have been released. Kernel K75 – aluminium interconnections, K76 – copper.

Magnolia – the code name of 1 GHz Athlon with kernel K76 to its output.

Thunderbird – the name of a kernel of processors Athlon released on processing technique of 0,18 microns with usage of processing technique of copper interconnections. On the chip 256 Kbytes polnoskorostnogo exclusive cache memory L2 are integrated. As a transitive variant some time it was released in form factor Slot A. However the main form factor is Socket A. The model with frequency of 1,33 GHz shows the big productivity on office tasks, than the processor of Intel of Pentium 4 with frequency of 1,7 GHz. The technological potential of kernel Thunderbird gives possibility of release of products with frequency to 1,5 GHz.

Athlon – the name of the processors created on the basis of K7 architectures, К75, К76, Thunderbird in variants Slot A and Socket A (Socket 462). The high-powered processors oriented to sector of computers High-End.

Duron – the name of the bar of the processors oriented to sector of computers Low-End. Are competitors of processors Celeron, however possess the smaller price and bolshej productivity at equal operating frequencies. Are constructed on a variant of kernel Thunderbird with cache memory L2 cut down to 64 Kbytes. Are released only in form factor Socket A.

Spitfire – the code name of a kernel and processors Duron.

Mustang – server variant Athlon. Cache memory L2 – 1-2 Mb, integrated into the processor chip. The processor is calculated for usage of the bus of 266 MHz and memories DDR SDRAM. Release is excellent.

Corvette – the code name of a transportable variant of kernel Mustang. It is renamed in Palomino.

Palomino – the code name of a kernel of processors Athlon which have come in the stead to Thunderbird architecture. Insignificant architectural changes for the purpose of improvement of high-speed potential of the processor are assumed. For example, as a part of a kernel the improved block of a branch prediction and hardware preselection from memory use. Processors on a new kernel will not support SSE2. The information that the pipeline will contain in kernel Palomino bolshee number of steps, does not prove to be true. Palomino will be faster, than Thunderbird, working on the same frequency. Socket A remains the main processor slot for 2-3 years, AMD corporation not namerena to change the physical interface of the processors. Palomino will work on the motherboards supporting bus EV6 with frequency of 266 MHz. In production of processors the processing technique of copper interconnections will be used. Low models are calculated for clock rate of a kernel of 1,533 GHz and above.

Morgan – the code name of a kernel of processors Duron. Differs from Palomino not only size L2, but also that will be made on processing technique with usage of aluminium interconnections.

Thoroughbred – the improved version Palomino created on processing technique of 0,13 microns. Prospective clock rate – 2 GHz. Output period – 2002

Appaloosa – the improved version Morgan created on processing technique of 0,13 microns. Output period – 2002

Barton – version Thoroughbred improved by usage of processing technique SOI (SOI – silicon-on-insulator – "silicon-on-insulator"). Usage of this processing technique allows to increase clock frequency approximately by 20 % and to reduce thus energopotreblenie.

Hammer – the set of 64-bit processors. Into it enter ClawHammer and SledgeHammer. The set of 64-bit processors Hammer is based on K7 architecture in which 64-bit registers and additional instructions for operation with these registers are added, and also new server instructions. Usage of processing technique SOI is possible. The question on support SSE2 is solved.

ClawHammer – first 64-bit processor AMD. Unlike Itanium, this processor will be oriented mainly to 32-bit instructions. Simultaneously with its output appearance of new bus HyperTransport (Lightning Data Transport – LDT), used for link with processors and input/output arrangements is expected. LDT should become not changeover, and addition to system bus EV6 or EV7. Support to two processors is provided. Prospective speed – 2 GHz and above. The "Know-how" – 0,13 microns, SOI. Output period – 2002

SledgeHammer – server variant ClawHammer. Support to eight processors is provided. The "know-how" – 0,13 microns, SOI. Prospective period of an output – 2002

Cyrix

6x86 – the name of processors Cyrix. For an estimation of productivity concerning Pentium processor used P-Rating, showing frequency on which it should to work to the processor of Pentium for reaching of the same productivity. P-Rating 6x86 made from 120 to 200 MHz. The L1 cache – 16 Kbytes. Frequency of the bus of the processor – from 50 to 75 MHz. The plug – Socket 5 and Socket 7.

M1 – The same, as 6x86.

MediaGX – deriving in the set of processors Cyrix. The first processor made on ideology PC PC-on-a-chip. To a kernel 5х86 controllers of memory and PCI have been added, the video accelerator is integrated into the chip with the frame buffer in base memory PC. In the last models the kernel 6x86 uses. In the chip-partner bridge PCI-ISA is realised and the sound is integrated. A PR-rating from 180 to 233 MHz, cache memory L1 – 16 Kbytes. It was made on tehprotsessu 0,5 microns.

6x86MX – processed for the purpose of reaching bolshej productivity a variant 6x86. Cache memory L1 – to 64 Kbytes. In structure of the architecture of a kernel block MMX has been added. There was a support of separate power supply. Frequency of the bus of the processor – from 60 to 75 MHz. A PR-rating – from 166 to 266 MHz. Processors 6х86MX were done also by IBM company. Their products 6х86MX had a rating from 166 to 333 and have been calculated for frequency the bus 66, 75, 83 MHz. Later, for marketing reasons, Cyrix has renamed the processors in MII, and IBM till the end of cooperation sold them under a brand 6x86MX.

MII – last processor Cyrix, has started to be made in March, 1998. Cache memory L1 – 64 Kbytes (uniform), L2 as usually for Socket 7, is on the motherboard and has size from 512 Kbytes to 2 Mb, working on frequency of the system bus. Supported sets of instructions – MMX. Uses a PR-rating. By production it was applied tehprotsess 0,25 microns.

Cayenne – the code name of the kernel used in Gobi and MediaPC.

Gobi (MII +) – the processor calculated for platform Socket 370. Supported sets of instructions – MMX, 3D Now!. The block of operations with numbers from a floating point is Considerably processed. Cache memory L1 – 64 Kbytes, cache memory L2 – 256 Kbytes on the chip, kernels of the processor working on complete frequency.

Rise

mP6 – The first processors of company Rise. Are intended for the notebooks using Socket 7. Differ very small heat release. Cache memory L1 – 16 Kbytes (on 8 Kbytes for data and instructions), L2 – from 512 Kbytes to 2 Mb, is allocated on the motherboard, works on frequency of the bus of the processor. The additional set of instructions MMX is supported. At an estimation of productivity of processors Rise, as well as Cyrix, uses a PR-rating making from 166 to 366 MHz.

mP6 II – the processors differing from the predecessors mP6 by that in the chip cache memory L2 in size of 256 Kbytes is integrated. Support SSE, productivity from PR-200 and above have been promised. However in August 1999 it has been declared cancellation of schedules on an output of the processor because of considerable rise in price after addition L2 in the chip.

Tiger – mP6 II for platform Socket 370. Cache memory L1 – 16 Kbytes, L2 – 256 Kbytes, working on clock rate of a kernel of the processor. Release is excellent.

Centaur

Winchip С6 – the processors oriented to cheap PCs. On productivity concede to the competitors. The bus – 60, 66, 75 MHz, a platform – Socket 7. Processing technique – 0,35 microns. Processors support a set of instructions MMX. Has quitted in October, 1997, worked on frequencies from 180 to 240 MHz.

Winchip-2 – The processors made on tehprotsessu of 0,25 microns. Cache memory L1 – 64 Kbytes (on 32 Kbytes for instructions and data), cache memory L2 – 512-2048 Kbytes is on the motherboard. Processors support sets of instructions MMX and 3DNow!. A platform – Socket 7. From Winchip С6 differ considerably accelerated operation with numbers from a floating point. There was a support frequency the system bus of 100 MHz. The first processor has appeared in November, 1998, frequency from 200 to 300 MHz.

Winchip-2A – Processors Winchip-2 with the corrected error in implementation 3DNow!.

Winchip-3 – Processors with cache memory L1 in size of 64 Kbytes (on 32 Kbytes for instructions and data) and cache memory L2 in size of 128 Kbytes on the chip, working on frequency of a kernel of the processor. Cache memory L3 – 512-2048 Kbytes, is allocated on the motherboard. Of 300 MHz and above were planned to an output in first half of 1999 with frequency. In connection with purchase Centaur by VIA corporation the output of processors has been excellent.

Winchip-4 – The processors, which release it was planned in the end of 1999 of Frequency – 400-500 MHz, and at transition to 0,18 microns tehprotsess – 500-700 MHz.

VIA

Samuel – the code name of processors and a kernel. As a basis kernel Winchip-4 which has got VIA in the inheritance from Centaur has served. Of 500-700 MHz work on frequencies. 0,18 microns tehprotsessa are made National Semiconductors and TSMC with usage. Processors use set SIMD 3D Now!. The Form factor – Socket-370. Cache memory L1 – 128 Kbytes. Have received name Cyrix III. Clock rate of a kernel – 500-667 MHz.

C5A – The same, as Samuel.

Samuel 2 – the code name of processors and a kernel, developed by group Centaur. Cache memory L2 in size of 64 Kbytes. Clock rate of a kernel – 667-800 + MHz. Frequency of the bus of the processor of 100/133 MHz, a form factor – Socket 370.

C5B – The same, as Samuel 2.

Matthew – the code name of the integrated processors. Incorporate kernel Samuel2 with integrated video and North Bridge components.

Ezra – the code name of processors and a kernel. Joint development of groups Cyrix and Centaur. First really new kernel VIA. Processors with support SSE. Cache memory L1 – 128 Kbytes, cache memory L2 – 64 Kbytes. Processing technique – 0,15 microns c transition to 0,13 microns. Clock rate of a kernel – 750 MHz with the subsequent growth above 1 GHz. TSMC has confirmed the information that it has made processor Ezra with frequency of 1 GHz.

C5C – The same, as Ezra.

Ezra-T – The code name of processors and a kernel. Compatibility on level of signals with Tualatin, that allows to use them in motherboards with the chip sets created under Tualatin. The Procedure 0,13 microns, aluminium interconnections. A cache memory memory L1 – 128 Kbytes, L2 – 64 Kbytes. Have smaller, in comparison with Ezra, energopotreblenie. Support MMX, 3D Now!. Clock rate of a kernel – from 800 MHz (6х133 MHz). Release is planned on the end of 2001

Nehemiah – the code name of processors and a kernel. Are calculated for operation at frequencies 1,2 + GHz. Cache memory L1 – 128 Kbytes, cache memory L2 – 256 Kbytes. Will support instructions Streaming SIMD Extensions (SSE) and 3DNow!. The pipeline in 17 stages, a supply voltage of a kernel 1,2 In, tehprotsess 0,13 microns with usage of copper interconnections, chip square – 72 sq. mm. The output is planned for 2002

C5X – The same, as Nehemiah.

Esther – the code name of processors and a kernel. Cache memory L1 – 128 Kbytes, L2 – 256 Kbytes. The pipeline of 17 steps. Clock rate of a kernel of 2 GHz. It is planned on second half of 2002.

C5Y – The same, as Esther.

SiS

550 – base model of processors of a series 550. As a basis the kernel mP6 from Rise with integrated video and chip set components has served.

551 – the model of the processor created on the basis of SiS 550, with support of flesh-maps and enciphering.

552 – the model of the processor created on the basis of SiS 551, with support of audio-and a video capture.

Transmeta

Crusoe – the bar of the processors oriented to transportable systems. Consists of models TM3200 (L2=0), TM5400 (L2=256 a Kbyte), TM5500 (L2=256 a Kbyte), TM5600 (L2=512 a Kbyte), TM5800 (L2=512 a Kbyte), incorporating integrated North Bridge components. Are characterised low energopotrebleniem.

Astro – a code name of high-powered processors with ultralow level energopotreblenija. The Operating frequency will reach 1,4 GHz at 0,5 W. In a basis the 256-bit architecture. Release of models is planned for 2002

Compaq

Alpha EV68 – a code name of high-powered processors with the architecture which is distinct from traditional х86. Tehprotsess 0,18 microns. Is based on kernel Alpha EV6. More than 15 million transistors. GHz model 1 is declared in 2001

Alpha EV7 – a code name of high-powered processors. Tehprotsess 0,18 microns with usage of copper interconnections. Is based on kernel Alpha EV6. More than 100 million transistors, a supply voltage of a kernel 1,5 In, power of a heat release of 100 W, frequency of 1,2-1,3 GHz, to 1,75 Mb L2, tank with 1439 contact electrodes. Usage of the integrated controller of memory is possible. Release of models is planned for 2002 In connection with purchase by Intel corporation in 2001 of divisions, patents and the processing techniques linked to processors Alpha EVxx, processors Alpha EV7 or Alpha EV8, probably, will be the last developments of this direction.

Alpha EV8 – a code name of high-powered processors with the architecture which is distinct from traditional х86. Tehprotsess 0,13 microns with usage SOI. More than 250 million transistors, a superscalar kernel (to 8 instructions for 1 clock tick), power of a heat release – 150 W, frequency from 1,4 GHz, cache memory L2 will roughly make 2 Mb, tank with 1800 contact electrodes. Release of models is planned for 2004 Probably, last development of this direction.

Alpha EV9 – a code name of high-powered processors with the architecture which is distinct from traditional х86. Tehprotsess 0,10 microns, 500 million transistors, frequency of 2-3 GHz. Release of models has been planned for 2006

Alpha EV10 – a code name of high-powered processors with the architecture which is distinct from traditional х86. Tehprotsess 0,07 microns, 1,5 mlrd transistors, frequency of 3-4 GHz. Release of models has been planned for 2008

QuickBlade – the server architecture with superhigh density of mounting. At the heart of the given architecture usage of processors of Intel with an ultralow supply voltage is planned.

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